An assembler! ...or, well, half of one.

A project log for risk-vee

An as-small-as-possible RISC-V implementation in Logisim.

Nicky NickellNicky Nickell 12/25/2016 at 18:310 Comments

I decided to (for now) forgo using the GNU toolchain for now so I can play with building my own. So far I have the output portion of an assembler done which is just enough to start writing test programs. The biggest program risk-vee has run is as follows:

addi r1, r1, 1
addi r2, r2, 5
addi r3, r3, 1
bne r2, r3, -4
sub r3, r3, r1
bne r3, r0, -4
bne r0, r1, -16

In a nutshell: count register 3 up and down between 0 and 5.

Not the most exciting thing in the world, but it did uncover a few bugs in the microcode. Branch instructions were using the wrong immediate format and comparing registers improperly (enabling a latch at the wrong time).

My desktop, which has an old i7 2700k running at 4.4ghz, was able to run the circuit at 3.8khz with a clock setting of 4.1khz in Logisim. I have a stable profile for 4.9ghz, but unless I go crazy and try to build a GPU the extra horsepower shouldn't be needed. If you play with the program above I am interested in hearing your performance numbers and your cpu+clockspeed. Right now the only two data points I have are my desktop and my little laptop which has an AMD e-350 underclocked to 800mhz (it ran slow and wouldn't even give me a simulation speed).

As usual, I uploaded a RAM image of the program above. At some point in the next few days I'm going throw everything up on github. Now that I'm actually writing code instead of designing a circuit we need version control.