Instruction Set Shuffle

A project log for Hardware Controlled 4 bit CPU

A hardware controlled 4 bit CPU based on lessons learnt from the TD4 and the CHUMP CPUs

agpcooperagp.cooper 12/21/2022 at 13:210 Comments

Instruction Set Shuffle

Having ADD and SUB in different op code pages seems wrong, as SUB (ACC = Value - 1) can be coded as:

Yes, the carry flag works.

The current op code set would be:

No saving!

To test for a value you could use:


A better set of op codes would be:

AND has been promoted over NAND as it can test for bit states:


This will be version 5.

Here is the simulation of up counting followed by down counting, then repeat:

The code for the animation is:

E0  PAGE 0           ; Select Op Code Set 0
20  ADD 0            ; Clear Carry
00  LOAD 0           ; Clear ACC
AF  SAVE F           ; Output ACC
A0  SAVE MEM[0]      ; Save to RAM
21  ADD 1            ; Increment
83  JNC 3            ; Loop1
20  ADD 0            ; Clear Carry
0F  LOAD F           ; Set F
AF  SAVE F           ; Output ACC
A0  SAVE MEM[0]      ; Save to RAM
41  SUB 1            ; Decrement
89  JNC 9            ; Loop2
20  ADD 0            ; Clear Carry
82  JNC 2            ; Repeat

The top level:

The ALU:

And control: