The TS3L501 arrived today. I hooked up the bare minimum in order to see if it works as the chips were much smaller than I expected and soldering 20, 38 gauge magnet wire patches didn't sound like something I needed to do in order to see if the theory works. I attached only the CS1, D0, MUX Select, and common lines for my test.

There is a 2ns delay time for data going through the MUX, at least as far as I noticed on the LA and compared it to the line that is also tied directly to MCU2. That is a small enough delay that makes this approach viable! 

So now that I have verified that I can use this MUX, I'm designing another prototype board. I think I'll go raw rp2040's this time to get access to all available gpio pins. The mux helps but I am not totally sure which control lines can be muxed with the data lines and which need to be available at the same time.

Control lines: CS0, CS1, A0, A1, A2 are all set before READ/WRITE state changes and can safely be muxed with the data pins.

DMARQ and DMACK (DMA lines), INTRQ, READ, and WRITE will need to be standalone on one chip and can't be muxed. Or at least I don't think they can be muxed. Data lines will need to be available during any READ/WRITE, INTRQ, or DMA signals. It might be possible to setup some more complicated circuitry to auto switch the mux when RD/WR go low and that would save me 1 pin. It would also introduce extra complexity and probably not worth it at this point.