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16 Bit CPU in Verilog HDL

A very minimal pedagogical 16 bit processor based on the Harvard Architecture

talha

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Files

pc.v v - 682.00 bytes - 09/13/2023 at 14:26		Download
README.md md - 236.00 bytes - 09/13/2023 at 14:26		Download
topmodule.v v - 1.22 kB - 09/13/2023 at 14:26		Download
register file.v v - 1.21 kB - 09/13/2023 at 14:26		Download
instruction memory.v v - 1.17 kB - 09/13/2023 at 14:26		Download

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