I decided to test the idea with a ring oscillator. After seeing that five inverters would oscillate in a SPICE simulation, I heated up the soldering iron and made this:
there are five inverters based on the original circuit:
each one has a 0.47uf supply bypass capacitor. The circuit starts to oscillate at about 0.4V, but is wildly unstable. At 0.8V, it draws 30mA with stable oscillation:
The oscillation frequency is 2.4 MHz, equal to a period of 420 ns. This implies a propagation delay of 42ns per inverter.
There are a lot of issues that would have to be solved before this becomes a usable logic family, but it's a start.
If we can figure out how to make either an AND or OR gate, we'll at least be logic-complete, then it's a matter of details.