Here's a first try at a NAND gate. I took @Yann Guidon / YGDES's advice and went series on the bottom and parallel on top. If it works, the project is a success in some sense - every other gate can be constructed from NANDs. I've only simulated it so far.
It's a straightforward adaptation of a simple CMOS NAND. I simulated the supply at both 0.8 and 1V, and it seems to work at either one, although a little better at 1V. The base resistors limit the input currents - these should have been on the inverter inputs, too. Because of the "stacked" input stage, the inputs are not symmetrical. For instance, here's the output voltage vs the top input with the bottom input held at logical 1 (1.0V):
With the bottom input high, the NAND gate works like an inverter for the top input. And it looks like a pretty good one. The results aren't quite as good with the inputs reversed:
Here, with the top input held high, the threshold for the bottom input isn't great. Still, if you specify the Vih parameter (minimum high input voltage) as maybe 0.65V, then it should be fine.
I think this should be workable as a logic gate. I don't know about performance yet.
If you add another inverter stage to "clean up" the output, you get an AND gate with very nice thresholds on both inputs. Here's the circuit:
and the output with the top input high and the bottom swept (the "bad' curve above):
The output inverter produces nice thresholds for both inputs; their transfer functions are now basically identical.