Yes, it was poor layout on the prototype. A long alligator lead used to pull one NAND input high had enough inductance to resonate with the input network and cause problems. I was able to simulate it in LTspice by adding an inductor where the long lead was. The yellow trace is the base of the upper NPN, and shows ringing like I saw on the hardware:
The 200 nH value was a complete guess - the actual inductance would depend on how I draped the alligator lead on the workbench, but the qualitative behavior was the same as I observed.
To fix the problem, I tied the upper input high with a very short wire. The circuit doesn't show the resonances anymore, but the propagation delay is still relatively long and somewhat sensitive to input pulse width. For instance, with a 1 MHz input signal, the propagation delay is around 16.5 ns, rising to 19.7 ns at 10 MHz:
On a longer timescale, the 10 MHz output still looks usable - I think you could go even higher:
The fact that this circuit had issues with long leads on a "DC" input made me wonder about the edge speeds - that's what determines how much you have to worry about layout. The conservative rule of thumb is that you have to treat wires electrically longer than 1/6 of the transition time as transmission lines and terminate them at one or both ends to suppress waveform-distorting reflections. So, I decided to measure the edge rates.
In the book, "High Speed Digital Design: A Handbook of Black Magic", Johnson and Graham describe five methods for estimating the rise time of logic signals:
- Differentiating the step response to yield the impulse response then taking the standard deviation
- 10%-90% direct measurement
- 20%-80% direct measurement
- Center slope measurement
- Maximum slope measurement
(1) is interesting but too involved for now. (2) and (3) are complicated by the ringing, overshoot and odd shape of the waveforms. That leaves (4) and (5), which measure the slope of the rising edge, either at the center of the edge, or at the position of maximum slope. I just used cursors to measure the slope somewhere around the middle:
The measured slew rate is 440 mV / 960 ps = 0.458 V / ns. According to this site, this is about half the slew rate of 74HC logic at 5V supply, which is about 0.9V/ns. But, the supply here is 1.1V, only 22% as high as the 74HC. According to Johnson and Graham, this translates into a CBJT rise time of:
The same calculation for 74HC logic at 5V supply yields 5.5ns rise time, which agrees with 5ns figures I've seen quoted elsewhere. So, CBJT logic has edge rates about twice as fast as 74HC. While at first this might sound good, it means complications for laying out projects with CBJT logic. Light travels 72cm in 2.4ns, so you might have to treat wires as short as 12cm as transmission lines (assuming velocity factor = 1). You could add some more parts to slow the rise time (a simple RC network on the output would do it), but it detracts from the simplicity of the design. Maybe you can just add an extra RC at the output when you have a long run to drive.