My RAM is asynchronous which means it can be written/read independent from the clock. This gives me trouble in my VHDL simulation. I found out that Vivado doesn't indicate when a signal glitches. I know Modelsim does. I was seeing my RAM contents getting changed at strange addresses when the write line was not changing. I knew this could be a problem since the control lines going into my RAM come out of combinational logic. Normally this is a big no-no, but I'm trying to cut corners. I may do something like gating the write signal with the clock, so it only changes on a certain clock level. This does fix the glitching in simulation. Gating with the clock is also a big no-no, but I'm still looking at bending the rules to keep things simple and not add too much extra logic.

However, I was also expecting Vivado to tell me when a signal glitches. Of course, it's possible there's an option to set, but I don't see a whole lot of options. I am thinking of trying out GHDL, but that's another investment of time to set it up and learn. If I get too many more problems with Vivado, I will start looking at jumping ship.