Today I merged new UART core into SoC. This new core have many benefits over the old one. For example:
- FIFO buffers for receiver and transmitter
- Two separated clock domains
- Better interrupt management
FIFO buffers are the win. Thanks to them, I can separate system interface from receiver and transmitter. Receiver together with transmitter are still running on 14,4 MHz to simply divide baudrate, but system clock can be raised significantly. At now I'm running at 80MHz without problems.
I also rewrote loader to work with new UART core, and tested it under emulator and inside of FPGA too.
New UART core is merged into branch "next" there is link to closed pull request.