I made the first video of the project:

and pushed everything to Github.

My next video was going to talk about pin planning, and then I started doing that... Before I started working on the project I naively figured that the Picozed would have more than enough processor IO to support the following peripherals:

• Ethernet
• WIFI
• USB 2.0
• I2C
• UART
• SD Card

Not a chance!

I opened up Vivado and selected the chip on the for the Picozed board, created a block diagram and dropped in a Zynq block on the page. When you open up that Zynq block you get this neat interface:

It shows how the processor is connected to the outside world as well as to the FPGA.

When you select the 'Peripheral I/O Pins' you get this:

In order to configure the processor to use a specific peripheral you just need to highlight it.

As an example the 'SD1' is selected on pins: 10 - 15, this will be used for the EMMC or SD card. If those physical pins don't work for your physical design, you can use the 'SD1' on pins: 22-27 but if you do you won't have access to 'Enet0' (Ethernet) so to use this you will need to make tradeoffs.

This information along with a lot of other configuration data is used to write the "Device Tree Source" for the Linux kernel, which configures the kernel to use those peripherals.

Unfortunately the Picozed board uses the Ethernet so if you don't want to use the Ethernet you are out of luck.

I thought about it for a while. Should I drop the WIFI in favor of the Ethernet. I ended up answering no to this. I think it would be more convenient for the user to have WIFI so I'm going to drop Ethernet and use 'SD0' for WIFI. I was thinking about a board mounted USB WIFI chip but they are hard to find.

I really want to have both the WIFI and SDIO. I'm hoping I can do this with a multiplexer or a 'chip select' but I don't know just yet. If I can get both the WIFI and SD card support I'll be very happy.

Either way the only way to accomplish this is to capture the entire Zynq chip on Enigma itself instead of using the Picozed connectors. This may not be that hard because the reference design is available and it's already in Altium so the process of adding a routed Zynq and DDR3 memory to my board may just be a matter of dragging and dropping it into my design and layout. It's not trivial but it's far from starting from zero.

Unfortunately this will drive up the price of the board! I was hoping I could get away with a 6 layer board but I think at minimum I'll need an 8-layer board to accomplish the routing of the DDR3 and FPGA signals. Not to mention the chip by itself is $209 where the Picozed module is $250!

I'll make my decision in the next video.

Dave