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A project log for LayerOne 2014 Conference Badge

Electronic Badge, Based on the Proxmark3 with different FPGA, SAM7 , SDCARD and OLED

charliexcharliex 02/18/2014 at 23:070 Comments

​rev3 board, rerouted and moved components around to try to be closer to final design and clean up noise, split ground planes.


Changed SPI's to use the hardware SPIs of the Cortex, they were all Software SPI before, adding all the names to the pins on the eagle schematic was a good idea!

Better signal paths for the AMPL_LO/HI and 13.56Mhz clock. they were a tad crazy on rev2

​Made sure GCLKS were used on the clocks to FPGA, the FPGA is more than able to handle the speeds the clocks we're using are at, but why not, less latency the Spartan 3 has barely any GCLK pins though.

​Added a jumper to select which ADC input, trying to figure out why there is upto 1.5V on sampling

​Added USB pullup, oops forgot that on rev2, because the old ESD protection diode pack had a built in 1.5KOhm resistor

​Corrected ESD protection wires on USB, had them flipped!

Added more test points and moved to the back of the board, trying to put vias in all the test points, even though this is via in pad, the reason i did it is because i want to make a "bed of nails" with pogo pins for automatic and debugging. Test points are fantastic, they're useful for testing and rewiring when you do an "oops". The idea being generate a new board with pogo pin holes in place of the test pads and have them run to an IDC or such, then cut that out on the CNC and clip it on, at least that is the idea!

Still a two layer board, if i can make it work at two layer, then all the better , though we will do a 4 layer for final, its a tough layout to split up the adc/digital sides since there is a lot of crossover.

Likely be :-

analogue
​ground
​power
​digital

or such.


​Code wise a lot more has been ported over, but we're stalled at the high speed ADC/FPGA to ARM  data transfer, hoping using Slave Mode SPI on the ARM will cure it, which means changing the FGPA code to use an SPI style CS instead of a start of frame like it is now.


I'm still thinking about adding a CAN bus transceiver since everyone's gone CAN bus mad recently, which is odd since i stopped really messing about with it a few years ago.


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