Prototype Board Design#1

A project log for InterNoC

A Network-on-Chip for the System-of-Systems Era Enabling mixed interface communication between embedded devices (MCU, sensors etc.)

chris-gkiokasChris Gkiokas 09/26/2017 at 15:100 Comments

In this first board design log the schematic design for the prototype is presented along with a BOM that will be linked in the project page.

The proto board will be used to support and verify the IP development and stand as a proof-of-concept for this project. The board will be designed using KiCad EDA and will be fully open under the CERN Open Hardware License: GitHub Page

The board will feature:

Overall the design is quite minimal and it follows mainly the artix7 reference designs with the interfaces in attached straight on the FPGA I/O banks. The board requires an external 5V power supply that can be provided either by a common DC Jack or 2 dedicated pins.

In all reference designs, of course a set of switching regulators is used to provide for the power rails, in our solution a set of LDO regulators was used to reduce BOM cost. The design specs followed closely those of the reference design providing two 1A capable rails of 1V & 1.8V for core and aux supply respectively and a 2A 3.3V rail for the I/O banks of the FPGA. As the TI TPS7A regulators have pgood and enable function the timing sequence was kept to spec using RC Delay to keep the ramp ups separated at approximately 10ms, inherently monotonic due to LDO nature.

Sequence simulation on Texas Instruments Tina-TI:

As in the reference designs the clock source is a 100MHz Abracon mems oscillator. The board also has 24 LEDs and two tactile switches to aid prototyping.

For the interfaces, while we thought about using level translation on the interfaces to increase the robustness of the board, the BOM cost with that many is skyrocketing so a simple Zener- resistor protection was used, the interfaces are 5V logic tolerant due to Zener action. The number of interfaces was decided purely upon how many 2.54mm pitch headers can fit on the edge of a 10x10cm square. The assignment of master and slave interfaces is not hardware decided of course and can be interchanged from the fpga, for that reason there are no external pullups.

Master Interfaces:

Slave Interfaces:

The main chip will be a Xilinx Artix 7 FPGA (XC7A35T-1FGG484C) and will be configured by JTAG with SPI flash configuration.

The BOM is linked here, however resistor values on the interface channels may change once the final trace impedances on the PCB are calculated, especially in the SPI interfaces where the clock speeds can theoretically be over 20MHz.