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A little explanation

A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 04/12/2022 at 20:090 Comments

It seems that the "main schematic" below, used as the project's avatar image, is not obvious enough, at least before zooming in enough.

@Ken KD5ZXG was not sure how to interpret/decypher the upper-left side.

So here is the explanation.

The home page says :

So this extra condition bit allows extensions for later, which could speed up some IO intensive algos, such as bit banging.  "B" means "bit", it's not a register per se (though it must be latched before to prevent race conditions) and it is user-defined wires. They could be front panel switches, synchronous or asynchronous data over 1 or 2 bits... or some condition inside the extensions blocks like UART ready/overflow/whatever status bits. I was a bit inspired by the CDP1802 on this, I admit.

The "Never" condition could be mapped to another bit/wire/condition but I don't want to play this game yet. ARM mapped this to an extension to the instruction set but YGREC8 is too young for that gymnastics yet.

... Maybe the 3=>8 rectangle is just a decoder?

Yes, once the condition for writing the destination register is determined, it is sent to the appropriate destination register for writeback. I should have made it clearer but the drawing is already pretty crowded :-)

The register set uses latches, and not DFF, to cut the register set power/area/cost in half. Imagine routing the clock signal to 64 bits and only updating 8 (or 16) every time... The diagram misses a buffer latch on the result datapath btw.

I'll try to summarize :

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I hope it helps.

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