A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

yann-guidon-ygdesYann Guidon / YGDES 11/12/2017 at 05:490 Comments

Beyond the typical GPIO, peripherals include serial transmission and timers for periodical interruption generation. These both deal with generation of a programmable frequency, and the #ProAsic3-Stamp  has a pretty fast 50MHz clock source : the quartz frequency must be divided.

This creates the need of high speed counters, which require at least 16 bits : 50MHz/2^16 = 762.93Hz. One timer is enough for feeding the serial port but longer periods require another timer, cascaded with the first one.

I have created another custom incrementer : INC16 is derived from the one used by PC. I extended it to 16 bits and I optimised it for speed, but the really interesting part is that I get access to the carry chain. This chain provides pulses that can then be tapped into for various purposes: I'm thinking about a binary predivider to feed other timers or clock sinks. The delicate part is how to avoid having another fanout, which drives a MUX or something like that.

A pretty unusual feature of the timers is they count up, not down. So if you want to generate a pulse after N cycles, you have to load the count register with 65536-N. This is easily calculated by negating all the bits during load, for example. Readback might give confusing values so I wonder if it's worth providing the feature.