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A project log for YGREC8

A byte-wide stripped-down version of the YGREC16 architecture

Yann Guidon / YGDESYann Guidon / YGDES 02/20/2018 at 01:460 Comments

One thing I've been thinking about : since the YGREC8 is a sort of subset of the YASEP ISA, wouldn't it be nice and easy to emulate the YGREC8 on the YASEP with a pipeline stage that performs binary translation of the YGREC8 instructions ?

UPDATE 20181014 :

Of course it would be more than a great feature.

In fact : it would be good to redesign the YASEP with that translation stage from the ground up.

There are two ways to do it :

In either case, some hardware is required to achieve this. Ideally, the least SW is required, the best !

Similarly : the #YASEP's instruction set should be straight-forward to emulate on the #F-CPU...


The YGREC8 instructions generally map directly to "long" YASEP instructions. A "Y8" mode bit must be set to enable the translation features, but most first-order details are pretty easy to translate :

There are quite some differences too :

Of course, the emulated Y8 can't access more than it can in a native implementation... But this emulation project is a good way to reboot the YASEP design again :-)

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