close-circle
Close
0%
0%

RISC-V Instruction Set Architecture

RISC-V is a free, open general-purpose instruction set architecture developed at UC Berkeley, designed to be flexible and extensible.

Similar projects worth following
RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at
the University of California, Berkeley.

Why RISC-V? Our goals in defining RISC-V include:

A completely open ISA that is freely available to academia and industry.

A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.

An ISA that avoids "over-architecting" for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.

An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.

Support for the revised 2008 IEEE-754 floating-point standard.

An ISA supporting extensive user-level ISA extensions and specialized variants.

32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.

An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.

Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.

A fully virtualizable ISA to ease hypervisor development.

An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.

What's Available?

Right now, you can download the final user-level ISA specification, and RISC-V software tools including aGNU/GCC software tool chain, GNU/GDB debugger, an LLVM compiler, an ISA simulator, QEMU, and averification suite.

The Sodor repository of educational RISC-V cores, written in Chisel is also available. The cores include a microcoded processor, an unpipelined processor, and 2, 3, and 5-stage pipelines. We plan to open-source our Rocket core (a 64-bit RISC-V single-issue in-order core) generator.

The zynq-fpga repository contains infrastructure for implementing Rocket cores on Zynq FPGAs, like the Zybo and ZedBoard.

To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser.

Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.

  • 1 × User-Level ISA Specification
  • 1 × RISC-V GCC
  • 1 × RISC-V GDB
  • 1 × RISC-V LLVM
  • 1 × RISC-V Clang

View all 6 components

View all 2 project logs

  • 1
    Step 1

    Try ANGEL, an in-browser RISC-V ISA Simulator that boots Linux

    You can try out RISC-V without even leaving your browser! Click here to launch ANGEL.

  • 2
    Step 2

    Install QEMU, a fast ISA Simulator

    Prereqs:

    • Linux or Mac OSX
    • C compiler (gcc)

    Download the QEMU Source, either as a zip from Github, or using git:

    $ git clone https://github.com/ucb-bar/riscv-qemu.git
    

    Now, cd into the riscv-qemu directory and run the following. You may exclude the prefix argument, in which case you'll find the qemu-system-riscv binary in the riscv-softmmu directory after building. Otherwise, replace [Location to place binaries] with the location in which you'd like riscv-qemu to be installed.

    $ ./configure --target-list=riscv-softmmu --prefix=[Location to place binaries]
    $ make
    $ make install # only run this if you specified a prefix above
    

    Next, you'll need to download two more files, the precompiled riscv-linux kernel and a disk image with the filesystem:

    At this point, ensure that the prefix location you specified above is on your path. If you opted not to include the prefix argument, enter into the riscv-softmmu directory, where the qemu-system-riscv binary is located. Once you've downloaded both of the above files, we can go ahead and boot linux:

    $ qemu-system-riscv -hda [Location of root.bin] -kernel [Location of vmlinux] -nographic
    

    You should see the linux boot messages fly by and will eventually come to an ash shell prompt:

    ...
    init started: BusyBox v1.22.1 (2014-07-19 16:30:20 PDT)
    starting pid 18, tty '': '/bin/busybox mount -t proc proc /proc'
    starting pid 19, tty '': '/bin/busybox mount -t tmpfs tmpfs /tmp'
    starting pid 20, tty '': '/bin/busybox mount -o remount,rw /dev/htifbd0 /'
    starting pid 21, tty '': '/bin/busybox --install -s'
    starting pid 22, tty '/dev/console': '-/bin/ash '
    BusyBox v1.22.1 (2014-07-19 16:30:20 PDT) built-in shell (ash)
    Enter 'help' for a list of built-in commands.
    
    / #
    

    Congratulations! At this point you've booted Linux on a simulated RISC-V system. To exit the system cleanly, you should issue the halt command inside the simulated system, and then hit Ctrl-a x:

    $ halt -f
    Hit Ctrl-a x to exit qemu
    

    If you'd like to learn more about riscv-qemu, see the Download page.

  • 3
    Step 3

    Build your own RISC-V Computer with a Zybo or ZedBoard

    How it works

    Both the ZedBoard and the Zybo board contain Xilinx Zynq chips with an ARM processor tied to some programmable logic. We'll use the ARM core to bootstrap the RISC-V Rocket Core that we'll run on the programmable logic. Once we've started the RISC-V core, the ARM chip will simply act to emulate devices on the Host-Target Interface Bus (HTIF), like consoles and disks, while the Rocket Core takes care of all the heavy lifting.

    You can obtain a Zybo or ZedBoard from various distributors online. From our experience, academic users can buy a Zybo for $125 or a ZedBoard for around $320.

    Instructions

    1) Connect the necessary cables to your board

    If you're using the Zybo, you can either use Ethernet + USB or just USB

    If you're using the ZedBoard, you should connect the power and either the USB or the Ethernet

    2) Download the appropriate package

    Download the appropriate package below, unzip it, and place the contents on the root of your SD Card

    Zybo RISC-V Getting Started Pack

    ZedBoard RISC-V Getting Started Pack

    Once you've done this, the file structure on your SD Card should match the following:

    SD_ROOT/
    |-> riscv/
        |-> root.bin
        |-> vmlinux
    |-> boot.bin
    |-> devicetree.dtb
    |-> uImage
    |-> uramdisk.image.gz
    
    3) Login to the ARM System:

    Insert the (micro)SD card into your Zybo/ZedBoard. At this point you have two options for logging in:

    1) USB-UART

    To connect over usb, do the following (the device name following tty. may vary):

    $ screen /dev/tty.usbserial-210279575138B 115200,cs8,-parenb,-cstopb
    

    2) Telnet

    You may also connect over telnet using ethernet. The default IP address is 192.168.192.5:

    $ telnet 192.168.192.5
    

    In either case, you'll eventually be prompted to login to the ARM system. Both the username and password are root.

    4) Start Linux on the RISC-V Rocket Core

    Once you're in, you'll need to mount the sd card so that we can access the files necessary to boot linux on the Rocket core. Do the following:

    $ mkdir /sdcard
    $ mount /dev/mmcblk0p1 /sdcard
    

    Finally, we can go ahead and boot linux on the Rocket core:

    $ ./fesvr-zedboard +disk=/sdcard/riscv/root.bin /sdcard/riscv/vmlinux
    

    You should see the linux boot messages fly by and will eventually come to an ash shell prompt:

    ...
    init started: BusyBox v1.22.1 (2014-07-19 16:30:20 PDT)
    starting pid 18, tty '': '/bin/busybox mount -t proc proc /proc'
    starting pid 19, tty '': '/bin/busybox mount -t tmpfs tmpfs /tmp'
    starting pid 20, tty '': '/bin/busybox mount -o remount,rw /dev/htifbd0 /'
    starting pid 21, tty '': '/bin/busybox --install -s'
    starting pid 22, tty '/dev/console': '-/bin/ash '
    BusyBox v1.22.1 (2014-07-19 16:30:20 PDT) built-in shell (ash)
    Enter 'help' for a list of built-in commands.
    
    / #
    

    Congratulations! At this point you've booted Linux on a simulated RISC-V system. If you'd like to learn more about the RISC-V FPGA Infrastructure, see the Download page.

View all 3 instructions

Enjoy this project?

Share

Discussions

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates