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Glue logic

A project log for STEbus Z8000

Interfacing an existing Z8000 design to the STEbus

KeithKeith 11/09/2021 at 23:080 Comments

The TTL chip glue logic inputs and outputs are:

Inputs  Outputs
AS      ALE to two 74F573 chips
!MREQ   RAM CS
B/!W    RAM_ODD !CS
A18     RAM_EVEN !CS
A19     RAM !OE
!DS     RAM !WE
R/!W    
A4      SCC !CS
A5      CIO !CS
A0      IDE !CS
!DS
ST0-3

Adding up to 15 inputs and 9 outputs = 24 i/o pins total. More than a 22V10 has.

The RAM active high CS output can be omitted by using MREQ in the active-low chip select equations.

The AS and ALE pins can be omitted if kept in an external inverter.

The CIO select output pin is not currently used (freeing one pin).

The steps above reduce the pin count to completely fit in a single 22V10 chip.

The SCC select output could be used to select a USB FIFO interface instead.

I have attached a first draft logic equation, but not tried compiling it yet,

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