FLEX, IO page moves, VHDL

A project log for HD6309 Singleboard Computer

Hitachi HD63C09 clocked at a blistering 3 MHz with a capacious 64K of RAM! Retroputing bliss...

tomcircuittomcircuit 05/25/2014 at 02:290 Comments

Since my hacking about with the hd6303 (the Hitachi version of the 6800) I've managed to keep in touch with a fellow hd6303 enthusiast, Daniel Tufvesson ( check out his blog at ). Daniel has been looking very deeply into the FLEX operating system for the hd6309, and he's come to the conclusion that there's really only one (big) roadblock that complicates porting FLEX to this hd6309 SBC: the I/O page is located at $C000. FLEX OS was mostly run on the SWTPC-09 ( read more about this vintage machine at ) and it has IO located at $E000. The SWTPC-09 has RAM all wrapped around the IO area, and the FLEX OS has program and data intermixed very freely. To untangle FLEX to work with a different memory map would be a LOT of work. Well, I think it'd be fun to have an OS, and I'm not about to write my own, so I guess I'll move the IO page to $E000. This involves no real hardware changes, thanks to the CPLD that handles all the glue logic.

Speaking of which...the last released CPLD version (1.2) sports about as much utilization as the EPM7128 will stand - something around 100 macrocells. Sure, there's 28 more, but routing to them becomes really difficult and the Quartus fitter just cries uncle and gives up. As I put together CPLD version 1.3, still pushing around 98 macrocells, I took a real hard look at the circuit that resulted from my VHDL code. This is most easily done using the RTL viewer feature in Quartus. What I notices was that the address decoder was really "lazy" and the implementation was a bunch of n-bit comparators - not very efficient. So, on a whim, I re-wrote the address decoder using only plan-vanilla, hand-minimized logic equations. I was rewarded with the total design implemented in 73 macrocells - a 25% reduction! That allowed me to clean up some other things that bugged me in the CPLD, so version 1.3 preserves some room for growth/fixes in the future.

So, coming soon is the CPLD 1.3 with ROM bank 1 from $C000-BFFF and bank 2 from $E200-FFFF. Each bank can be switched out for RAM. Writes to the ROM space will always write to RAM, so it's easy to copy ROM to RAM; just read and then write each byte back to its original location - no need for a page buffer elsewhere in RAM.  Of course, this means that I need to do some changes to the MS BASIC, and the monitor program, to accommodate the new I/O page location. Moving can be a pain!