one shots... revisited.

A project log for sdramThing4.5 "Logic Analyzer"

An AVR, 128MB SDRAM DIMM, old laptop LCD, and a handful of TTL chips -- 30+MS/s 32-channel logic-analyzer interface for an analog 'scope

Eric HertzEric Hertz 03/31/2015 at 11:360 Comments
duh. seriously. duh.

Even without the cleverness of the single-instruction one-shot... why didn't I think along these lines...?

Of course, I should['ve] recall[ed], that the whole point of my AVR-LVDS-LCD project is to use the PWM signals (with PLL) for *exactly* the sort of purpose needed in *this* project for one-shotting.

Well, there are a few limitations:

That said... Something could've been done, likely... with the PWM316, maybe...? It's an EXPENSIVE chip, though, last I checked.

Or... I might've been able to replace all that one-shot logic with two Tiny85's or a Tiny861, which I do have in-stock.

Plenty of thoughts... but here's one anyhow:

The SDRAM clock could be generated by a dedicated PLL-based timer set to FastPWM-mode with E.G. a Match-value of 1 and a Top-value of 2... THIS IS HOKEY without knowing your chip:

Different PLL-based devices actually act differently with low match/top values... (I did a lot of experimentation with this in AVR-LVDS-LCD). E.G. one device matches *after* the matching-count is *left*, another matches *when* the matching-count is *entered*. Further, because of this, some devices *can't* have a match/PWM value of 1 timer-count... In that device it's 0,2,3...

So, if I recall correctly, some devices could actually toggle, with Fast-PWM, at 1/2 the PLL frequency (so 4x the AVR clock?), whereas others no faster than 1/3rd, which wouldn't be square. That, then, driving the SDRAM, would limit the SDRAM/AVR clock-ratio (which, at some point, I really am hoping to bump up to 4:1 maybe higher... Though, it's not the ratio that's important, but the overall SDRAM clock-speed... and 30MHz, now, seems to be the limit... I've had several of the PLL-Based AVRs' PLLs running at ~128MHz, which even at 1/4th--for the sake of squarifying the PWM/SDRAM-Clock output--would still be faster than I'm currently getting...).

But, basically, this method probably would've removed the necessity for *all* the additional circuitry in sT4.0 (one-shots, clock-divider... even the crystal-oscillator/buffer).

Anyways, it's funny this concept hadn't even come up as an option when thinking about this project... seeing as how much time I spent on something not unlike it not even a year ago.