Don't have instructions that can run only in certain "modes".

I know many CPU do it, even RISC-V, but I can't find a decent reason to accept this.

• It's a slippery slope : you'll want to do more and more.
• It's a waste of instruction coding space, which also reduces the overall coding efficiency.
• It increases the decoder's complexity.
• What does an instruction do that the Special Registers can't ?

Remember : Special Registers are where all the configuration, and protection, occurs, so there should be only two instructions that enforce "capabilities" : GET and PUT. They, and only they, clear the pipeline and ensure serialisation, trigger a trap/fault if the address falls in a forbidden range.

The SR space can grow while keeping the very same management opcodes. You don't need to change the decoder if you add features, it's all in the SR circuits.

KISS, guys.