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A project log for PDP - Processor Design Principles

Distilling my experience and wisdom about the architecture, organisation and design choices of my CPUs

Yann Guidon / YGDESYann Guidon / YGDES 02/01/2018 at 23:004 Comments

Damnit.

Accumulators are so 20th century.

But how many ?

Usually, a good rule of thumb is to use as many as your register width.

8-bits => 8 registers.

16-bits => 16 registers.

You see the pattern.

As to why this pattern exists, it's just a heuristic. Depending on the application and other constraints, this can change but these values are a good average for scalar processors.

Discussions

alan_r_cam wrote 02/03/2018 at 00:33 point

Yeah, the ARM format of combining an 8-bit value with a 4-bit shift is more elegant. Deliberately limiting 8-bit and 16-bit functions to the first 2 registers helps if you want to implement functions like ARM parallel arithmetic (byte-wise or halfword-wise add, subtract, exchange, sum of absolute differences)

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alan_r_cam wrote 02/02/2018 at 00:37 point

It also helps, with large registers, to split them into multiple smaller segments. Example: AH and AL are the upper and lower half of AX. 

Trouble is - the more you split up the registers, the more bits you end up using to reference them in your instruction set. So maybe you don't make EVERY register addressable in this manner.

32 bits => 32 registers. If the lowest 2 registers can be broken in 8-bit segments, that's 8 registers right there. Make lowest FOUR registers also available as 16-bit, and you have 8 more (16 total). Add 32-bit mode, and the lowest four registers account for 20 out of 32.

Final result: 32-bits => 16 registers (with 16-bit and 8-bit register support )

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Yann Guidon / YGDES wrote 02/02/2018 at 04:05 point

I... beg to differ.

This sort of hack creates all kinds of problems in the datapath, because you have to shift data all the time and a shifter adds latency in the critical datapath. The core runs slower...

Anyway, that's an excellent subject for a new principle :-)

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Samuel A. Falvo II wrote 02/25/2018 at 07:00 point

This sounds like what Zilog did with the Z8000 and Z80000 processors.  These are awesome CPUs, and I hope to replicate one in an FPGA some day.  But, I agree with Yann -- it's just straight up awkward to deal with in hardware.  Zilog had the benefit of multi-cycle instruction execution rates; however, their processors never went faster than 10MHz last I recall.  (Z80 being an exception, but only because of die shrinks.)

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