How should the IRQ be handled ?
Early microprocessors had a fixed-size, fixed-address table of addresses that point to user code. It's a compromise that worked rather well back in the days but today's architectures have evolved. Old problems must now be solved because the relative latency of main memory has skyrocketed.
Today I advocate for 2 things :
- Store not a pointer, but instructions directly. This is inspired by the ADSP2106x family that stores 4 instructions in the Interrupt Vector Table. Instead of 4 (which was suitable for the fast onchip SRAM), I'd recommend to have one or two cache line worth of instructions. The idea is to start prefetching the next cache lines from the real interrupt handler, while doing critical housekeeping (such as state backup) and early processing, if any.
- Set the start of the vector table in a register that is reset to 0 (to point to startup ROM) then changed by the operating system to a table built in RAM. This solves the old dilemma of "should the IVT be in ROM or RAM ?"