How should your core be clocked ?
- DFF are practical and very clean but take some silicon space.
- Transparent latches use half the transistors but twice the routing resources because you now need two clock networks that MUST not have jitter or phase noise (ask Seymour Cray about this, when designing the Cray 2 or the Cray 3).
So yeah, it depends. My approach is to design with classic DFF with a 4-stages pipeline to allow an easy transformation to 4-phases clocking, which has some advantages when you can control your technology very tightly.