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The First Four Two-Input Gates

A project log for Tern - Ternary Logic Circuits

A series of ternary logic gates and higher level components implemented in the real world.

mechanical-advantageMechanical Advantage 07/25/2015 at 09:210 Comments

The first four two-input gates are done! They take a bit of explaining but are roughly equivalent to AND, OR, NAND, and NOR. The reason I say they are only approximations of those familiar binary gates is because the words AND and OR (and the phrases NOT AND and NOT OR by extension) are meant to be descriptive of the binary truth tables for those gates. Unfortunately they fall short of describing ternary gates. Allow me to demonstrate with the binary truth table for an AND gate.

ABOut
000
010
100
111

The output is high when A AND B are both high. The name of the gate describes how it behaves. Ternary gates are significantly more complex, and those binary names break down because they do not adequately describe the function of the gates or the name could be used to describe many different gates with similar truth tables. Here is the ternary truth table for the gate most closely approximating AND.

BBB
-0+
A----
A0-00
A+-0+

Okay, the formatting doesn't look so good, but the first row of "- 0 +" on top is the "B" input and the first column on the left is the "A" input. The 3x3 square in the bottom right is set of 9 possible results for the given A and B inputs. Example: If input A is 0 and input B is +, the result is 0 (far right column, second from the bottom).

As you can see, calling this gate AND is somewhat accurate because if both inputs are the same, the output will be the same as the two inputs. Unfortunately AND doesn't cover many of the other conditions. If A is a 0 and B is a +, the result is a 0. Obviously we need more accurate names, so here they are:

Remember that the simple inversion (Monadic gate 5) leaves 0's alone but swaps -'s and +'s.

If you look back at the binary truth table for AND, you will see that the more general name Min works just as well for the binary gate as it does for the ternary one. The same is true of the other three examples here.

The Antimin (NAND) is two monadic 5's (simple inverters) with their outputs tied together. Max (OR) is two monadic P's (buffers) with their outputs tied together. Min (AND) is just an Antimin who's output has been passed through a simple inverter and Antimax (NOR) is a Max gate passed along to a simple inverter.

Now is a good time to mention that even these conventions are not standardized. For example, one source on the internet who was investigating ternary universal gates used the term NAND to describe a different gate entirely. His quite reasonable logic was that the basic description of NAND was "True when inputs differ, else rotate to next value" and assigned that to a ternary truth table where all outputs were + except for when both inputs were + (output would be -) or when both inputs were - (output would be 0). His work is here and is quite interesting. My terminology continues to be based on this.

Enough wordage. The schematics and truth tables are here.

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