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The Elusive Sum Gate

A project log for Tern - Ternary Logic Circuits

A series of ternary logic gates and higher level components implemented in the real world.

mechanical-advantageMechanical Advantage 10/15/2015 at 07:480 Comments

So I've been working on the Sum gate off and on for a little while and it's been a tough one. First it took me a while to find a combination of monadic gates that would give me the appropriate truth table. I won't bore anyone with the details but I worked out that (2 AND B) OR (6 AND P) OR (K AND 7) would do the trick. This would only take 8 comparators if I omitted the full P gate and just used a diode in its place (P gate is just a buffer) and used wired AND's and wired OR's instead of full gates. This did work after a fashion but the breadboard became so complex that just building it without errors was time consuming.

Unfortunately, it only sort of worked. There were just too many diodes interacting with too many other diodes to get really acceptable and stable voltage levels at the final output. A "0" output might be as high as half a volt and a - could get up to -3 when it should be -5. The +'s were mostly okay, but it was a bit of a mess overall. I was definitely experiencing too much voltage drop across various groups of diodes, but I think I also ran into excessive reverse leakage current in one particular spot. Long story short, I need to replace some wired logic with more comparators to make this sucker work reliably. That means 10 or more comparators for a single gate!

I really need to find another solution that isn't just cheating with a microcontroller to simulate the ternary logic.

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