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A project log for Tern - Ternary Logic Circuits

A series of ternary logic gates and higher level components implemented in the real world.

mechanical-advantageMechanical Advantage 01/12/2016 at 08:320 Comments

I guess I'm going to learn some analog design on this project even if I have to do it kicking and screaming the whole way. I just tested out using a single Op Amp to implement monadic P, the ternary buffer by configuring it as a voltage follower/unity gain amplifier. I also built a monadic 5, the "simple" ternary inverter with two resistors and an Op Amp configured as an inverter. I really should have learned this stuff in "Baby's First Electronics Handbook", but I never had any formal education on the subject so it was a surprise to me. This is nice because I was implementing P gates and 5 gates with two comparators, three resistors, and two diodes each.

I have also decided to stop fooling around with trying to build ternary latches out of comparators. I have successfully built all sorts of bistable circuits using feedback loops but have been unable to implement a "simple" ternary SR Latch because there is always one or more seemingly valid inputs that mucks the whole thing up. I've been close to successful with three different designs but it's just not coming together. I also don't feel too bad about it because it's actually a solved problem already. FLASH memory uses up to six different voltage levels to store multiple bits per memory element so I know it can be done. I just haven't figured out a way to do it with the materials at my disposal.

Nevertheless, I'm not going to go full dark-side and cheat with binary digital electronics (like an ADC followed by a DAC) but have instead placed an order for some sample-and-hold I/C's (LF398's specifically). These aren't true latches because they will lose their memory over time due to leakage current. If one were storing a -, it would maintain indefinitely, but a 0 or plus would droop down over time. The LF398 claims a 5mV/Sec droop rate if you use a .1uF polystyrene capacitor so if I stored a + it would take about 13 minutes to droop below the 1V threshold that would degrade it into a 0. If I stored a 0, it would only take about 3 minutes to droop below the -1V threshold that would degrade it into a -. I'm sure this is going to be irritating during design and testing, but I can't imagine anything I would prototype taking more that 3 minutes to use a stored value.

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