I've been very carefully and very methodically going through every failure mode I can work out for two possible flip-flap-flop circuits. One uses two comparators as latches with a bit of encoding and decoding circuitry before and after the latches to combine their outputs appropriately. The other uses comparators for inverting purposes and is a bit more like a traditional binary NAND or NOR flip-flop. This also requires some encoding and decoding circuitry to handle the inputs correctly.

The thing I'm seeing that may be a fundamental design flaw is my voltage-to-logic mapping. It seemed quite reasonable to assign the lowest voltage a logical value of -, the intermediate voltage as 0, and the high voltage as +. This appeals to our "more is better" mindset and seems like a natural extension of existing binary logic levels. However, there is a fourth state to consider; High-Z. In a binary system, the closest logical approximation to high-z is 0, the "off" logic level and it also happens to coincide with the 0 voltage level, no voltage. In a ternary system, the closest logical approximation to high-z is also 0, the "undefined, uncertain, don't care, doesn't matter" logic level. Unfortunately, high-z is always the lowest possible voltage level which, in my case, has already been assigned to the logical negative.

This is not the kind of flaw that prevents progress or breaks the whole project, but it does cause some headaches and awkward logic. Because the assignment of a logic state to a voltage level is entirely arbitrary it would actually be a better design decision to assign the lowest voltage level to be logical 0 so that it coincides with high-z. - and + would then be the intermediate and high voltage levels.