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Memory Schematics

A project log for Tern - Ternary Logic Circuits

A series of ternary logic gates and higher level components implemented in the real world.

mechanical-advantageMechanical Advantage 02/17/2016 at 08:290 Comments

Here is the first revision of the D Flip-Flap-Flop. It lacks any asynchronous inputs such as preset or reset and it lacks a complementary output so it is pretty bare-bones.

Here is an update to the SR Latch schematic. It just corrects the resistor value on the final output.

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