OK, so darn-near every register says something like "If you're using a peripheral-clock-divisor of 1:1, then do not write this register in the instruction immediately following writing this value"

...

Here's a quote from the datasheet:

When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

I have no idea what to search for, search-fu-fail, but it seems like it must be a common-enough thing...

Can we rely on xc32-gcc to make sure this never happens?

The obvious solution, not knowing, is to use a slower peripheral-clock (e.g. 1:2), but yahknow, sometimes yahs wants the speed, or need a ratio that's not 1:2^n where n>0, or something.

Has anyone run into the 1:1 PBCLK being an issue?