Ported over ZPU Avalance 32 bit CPU (not sure if will use it yet but its a good exercise)

Its a pure microcode implementation of the ZPU architecture, I've removed some of the options to fit 32bit BRAM vs the Xilinix 36 bit and generally make it smaller and easier to mod.

With a small internal RAM, the microcode ROM and the ZPU core itself its using

IOs 7 / 96

LCs 1119 / 1280

DFF 236

CARRY 75

CARRY, DFF 3

DFF PASS 159

CARRY PASS 2

BRAMs 9 / 16

GBs 0 / 8

Just fitting so far in a 1K ICE40, however we don't yet have a UART or a program ROM so further optimisations will be needed for it to be useful.

I think I can reduce the size of the microcode ROM by a fair amount, but doubt that will help number of logic cells used, that will require changes to the core itself.