I patched in the T80 processor, a 4KB ROM (empty apart from a JP 0 at the end), a 1KB SRAM and a 16450 UART today. It took surprisingly little fighting to get it to synthesise, copying mostly from the "DebugSystem" toplevel supplied with the T80 tarball, although when I started to connect up the 'A' port of my dual-port display RAM, it turns out that the Cyclone II FPGA I'm using doesn't actually support dual-clock, dual-port blockram, even though the Altera software initially says it does! [*] I also found yesterday that I can't create PLL components, even though the chip does have two clock managers, which is a problem for the pixel clock change.
New problems then:
- Find a way to prove the Z80 is actually running. LEDs on the A11/A10 lines don't appear to be cycling, with a roughly 1.5MHz CPU clock. Maybe I need an even slower clock. Once I can see the bus moving, I'll add the row of blinkenlights on the FPGA board as an I/O port.
- Figure out how to get data from the Z80 into display memory. Could this be using more I/O ports and some registers to track the cursor and write data? The screen doesn't *have* to be memory mapped...
- Work out the counters to centre and mask the 80x25 display in the 800x600 screen, since I'm apparently stuck with that.
Good news is that everything (CPU, UART, VGA, misc) fits into about 2700 LEs, assuming that Quartus isn't optimising anything away. Also, the flash attribute works as expected.
Testing the UART will require a working CPU, and also the external interfacing that I've been putting off wiring up. That will also get me 16 colours though, and a PS/2 port.
[*] Specifically: dual-clock, dual-port with different sized ports. I use 8-bit on the z80-facing port A, and 16-bit on the VGA port B, to fetch the character and attribute bytes in one shot. There is probably time to do two 8-bit fetches there.