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Address decoding II - electric boogaloo

A project log for FPGA Serial Terminal

Instant-on VT100-style serial terminal implemented in minimal FPGA board, with VGA display and PS/2 keyboard.

Howard JonesHoward Jones 09/21/2015 at 22:250 Comments

I wrote some quick assembler loops to blast the display RAM with characters, and it was strangely lumpy. I eventually figured out that the counter that I was pushing onto the stack to make room for another counter (one for rows, one for columns - the handy Z80 loop instruction (DJNZ) only works on a 8-bit register) was not actually being saved anywhere. So the lumpiness between bursts of update was while we waited for the Z80 to go all through the rest of the memory map trying to write before coming back to display RAM.

With that fixed (same error as the display RAM decoding, d'oh), the stack works, and the screen updates are really fast. I also got my dev board's LEDs hooked up to a Z80 I/O address so that software can signal status.

Finally, I started on a build script. It will turn into a makefile, but for now a batch file will assemble the Z80 ROM, pad it to 4K, convert it to intel-hex and tell Quartus to rebuild the FPGA image without synthesis. That all takes about 4 seconds instead of much longer for VHDL hardware changes.

I've also been looking around for a nice small laptop that's old enough to be worthless to normal punters, so I can get a cheap one on ebay. It needs to have a known LCD screen and either a documented or brain-dead keyboard ideally. I like Lenovo keyboards, so perhaps an old Thinkpad X? Failing that, my beloved 12" Powerbook G4 might be a candidate.

Back to the serial port now...

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