Redesigned layout in ISE

A project log for FPGA computer

I am building a (currently) 64k RAM computer with an FPGA. Now with lots of pipelining!

dylan-brophyDylan Brophy 08/01/2016 at 01:040 Comments

I decided things should work better if I broke my project into mini projects, tested them, and included them into the main project. This seems to have worked very well. I also made this change so that if I made another version of the design in another ISE project, It would be easy to make backwards compatible and\ work together.