Wow, it's been almost two weeks since I posted! I've been through hell and back.

After getting the simple LED blinker working with the open-source myhdl+yosys+arachne-pnr toolflow, I decided to take one of my existing designs and port it to the CAT Board. I chose the driver interface for the StickIt! LED digits board because I could attach that directly to one of the PMOD sockets on the CAT Board for testing purposes.

The driver uses eight tristateable outputs to control eight seven-segment LED digits. Forcing a high level on one of the outputs powers the common anode of one of the digits. Driving a low level on one or more of the other seven outputs will pull down the cathodes associated with those segments so current will flow and make them light up. The drivers for the rest of the segments are placed in the high impedance state so no current flows and the segments stay dark. Meanwhile, all the other digits stay completely dark because their anodes are either pulled to ground or in a high impedance state. After the pattern on the first digit is displayed, the next digit is activated by powering its anode and placing a pattern of low levels and high impedances on the other seven outputs. A stable pattern of eight characters is displayed by repeatedly cycling through all the digits.

The first challenge was to recast my VHDL code for the LED driver into MyHDL. I had an academic understanding of MyHDL, but that's quite different from actually constructing something that compiles, simulates and synthesizes into an FPGA. Obviously the syntax of MyHDL is different from VHDL, but you also have to re-learn how a design should be organized and partitioned for a new language.

One of the challenges I faced was the heavy use of tristate outputs in the design. MyHDL supports tristate buses, but it doesn't allow bits within a bus to be individually tristated. So I had to break the eight-bit LED driver bus into eight individual signals, which made it more cumbersome to handle since loops couldn't be used.

The MyHDL compiler converts MyHDL source code into Verilog or VHDL that is passed to the synthesis tools for a particular FPGA. But I found the Verilog and VHDL code for the tristate outputs wasn't actually connecting them to the internal logic in the driver. This problem was eventually resolved by attaching each tristate port to a dummy signal inside the driver code so that the port looked more like a true I/O port. It was easiest to implement this fix by building a separate tristate module and instantiating it eight times, once for each output. More cumbersome code.

I attempted to clean the code and make it more parameterized by refactoring it to use loops. While this worked in simulation, and was convertible into Verilog, the yosys synthesizer choked on it because it was, in fact, not synthesizable. So I had to remove the loops and use a more "unrolled" coding style. More cumbersome code.

Finally, I designed some code to send inputs to the LED driver and display a pattern of eight characters. Unfortunately, using an array of byte-wide signal vectors for the characters led to some strange errors. Instead, I had to use a single 64-bit vector with each eight-bit field representing a character to get the behavior I wanted.

After all was said and done, I finally got the LED driver to work: