So I found that old stash of pulled SRAM chips.
Each of these chips is 256K bits / 32K bytes at about 15-20ns, way faster than needed, but it's handy for the prototypes.
The YASEP16 is a 16-bits computer so pointers can access 64K bytes, actually 32K words of 16 bits (the LSB is handled in a specific way but that's explained elsewhere). Each memory bank needs 2 32K chips but since I chose to implement dual port memories, I "shadow"/clone the data so 4 chips are required.
3 memory spaces exist so overall, with this approach, 12 chips are required.
Dual ported memories are a common feature in FPGA. This was not a luxury that people could afford "back in the day" (except maybe some of Cray's customers).
The YASEP architecture does not force a precise memory layout so it's more a matter of convenience and compromises with the available technology.
Another option is to use a couple of IDT7132, dual-ported 2K*8 SRAM, which are smaller and make it a bit easier to write to the memory, but the capacity is smaller and there is still the requirement to multiplex one of the data buses during the write cycle...