In a precedent log (What chip(s) for the ALU ?) there was the question of implementing the ADD instruction (all other ASU opcodes are derived from this). I have found some MSI and LSI chips for this, I even considered using Flash or SRAM for this purpose (128K*8 for 8+8+carry) but it doesn't fit with the spirit of the project.
I finally found satisfying explanations at http://integrated-circuit-course.blogspot.fr/2015/09/adderscarry-look-ahead-adder.html
I like that it is well organised and I can almost "see" the DIP chips: one 74HC08 and one 74HC86 for the top row, one 74HC86 for the bottom row, generously spray more HC08 and HC32 for the OR, with other references for the higher input counts (74HC21 dual AND4 and the like, find more at https://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits)
The proposed construct is interesting, the fanout is reasonable and the bottom picture shows that a 16-bits adder is made of 4+1 Carry Lookahead logic blocks.
I don't see where this circuit originates from (I find no reference in the blog) but I see it is very similar to others I see in datasheets, but that are less clear (probably too optimised). For example the right-most AND2 of the above picture is duplicated/redundant.
I don't think I will use this for this project version but I will certainly play with it in a related project that explains every gate and signal of the circuits that the Discrete YASEP uses.