I know my updates on the project have been slow, but I really am working on it.  It's been a bit of a challenge given a bunch of headwinds, but I'm excited to report that I've made some significant progress after a lot of refactoring work.  I have unified the code for a bunch of the different dev boards I've been using, and so now in theory the same code will run on at least the DE10-standard and DE2i-150.  The MAX10-lite hasn't been tested yet, but will probably work as well, even with the limited onboard memory resources.

In addition to the SoC code itself, I also spent a lot of time bringing the toolchain up to date.  So now I have branches off of the master branch of gcc, binutils, and newlib which are current as of a week or so ago and appear to generate proper code.

There's also a lot of work that's been done with verilog and the unit tests for both the "microcoded" and the pipelined version of the Bexkat CPU.  They both run the same tests, and get the same results - with one exception.... exceptions.  :-)  The issue is that my original ISA pushed both the CCR and the PC onto the stack before jumping to the ISR, and for a pipeline model that's not ideal.  I'm thinking about a redesign that will require the ISR to push and pop it, but I haven't implemented it yet.  Until then, technically the microcoded CPU is the one that works correctly, since the other just ignores the CCR.

I'll be doing another push of the code to the public github repos in the next week or so, which should give a picture of what's been done.