The logical architecture of the baby is a 32-bit serial machine with a 100 Khz master clock. In addition to the main Williams tube it has two addition tubes which are used as follows.

• The Accumulator
  • used to store the intermediate results of calculations.
• The Control Store
• contains the Program Counter and the Present Instruction, a copy of the instruction being executed.

The instruction format is extremely simple. Only 8 bits of every 32-bit word are used. The lower 5 bits of each word contains a store address, and there is a three-bit op code in the middle. These get copied into two latches, which are called “staticisors” in the documentation. These are known as the “L-Stat” and “F-Stat” in the baby documentation. Obviously a 3-bit op code only allows eight separate instructions, but actually only 7 are used.

The execution of each instruction is divided into four phases which are called “Beats” in the original documentation. Each beat is 36 clock pulses long, 32 correspond to accessing the bits on the face of the Williams Tube during the forward scan, and four to allow the beam to return to the left hand side of the screen. As the beam is suppressed during this period these four beats are known as the “Black Out” period.

The means each beat takes 360 microseconds and each instruction takes 1440 microseconds. I therefore created a waveform with a period of 360 microseconds, but with a highly asymmetric ratio of 320/40 to manage the beats. The four beats are labelled Scan1, Action1, Scan2, Action2. The operations during these phases are as follows: -

• SCAN1
  • Increment the program counter.
  • Refresh the store
• ACTION1
  • Read the next instruction from store and save in the “PI” register
• SCAN2
  • Copy the address and function code from the “PI” to the L-Stat and F-Stat
  • Refresh the store
• ACTION2
  • Execute the instruction

Note that in order for the storage tubes to be refreshed the four phases occur even if the stop/run switch is set to “stop”. Instructions are still fetched, but the stores are never updated.

When I started implementing the CPU I had one design goal, and that was to make it run at the same speed as the real Baby. So in order to implement this in the FPGA I created a master clock with a period of 360 microseconds and a 320/40 on-off ratio derived from the on-board 50Mhz clock. As I was implementing a parallel machine not a serial one, I did not need to replicate the 100Khz clock.

• Accumulator
• Program Counter
• Present Instruction
• L-Stat
• F-Stat

and added VHDL code to mirror the operation of the full sized machine in each of the Phases. As the RAM that represents the main store is dual-ported this code operates independently of the VGA logic. The VHDL code for the CPU takes up just under 100 lines of VHDL, excluding the comments. In order to test the code, I configured the project to pre-load a demonstration program into the memory, connected the Nexys 2 to a standard LCD VGA Monitor and loaded the new logic into the FPGA. Much to my surprise the program ran first time. You can see a video of it running here:-So I now had an operational Baby that would run just one program. I did not even have a stop/run switch. I needed to add the other hardware to make the BabyBaby a close replica of the full sized machine