Time for a brake so here are some screens of my board layout progression

February 11th: After placing components down with some trial and error to see how well things fit, I opted to route the most challenging piece at the time: my SRAM frame buffer and octal d-latches. Initially setup to where the longest traces on the top and bottom were roughly the same.

February 17th: Decided where the mDP receptacles would go and the upright Micro-B USB ports for analog inputs

February 18th: Though research showed it may not be critical as my highest operating frequency is 80 MHz and 1/20th of the associated wavelength is ~187 mm, best practices says one should have trace lengths match. It's more complicated in the design since I have multiplexed data on the PMP bus to match pin to latch, pin to SRAM data, and latch to SRAM address and assure they're the same lengths, I opted for a cross between all and nothing and matched the lengths of all three trace segments as if they were one. I also determined by rough estimate that I would be able to size D-DAQ to be no larger than 3"x3".

February 25th: Despite having a huge car battery and alternator for a power source, I wanted to make D-DAQ very energy efficient. Previously I had spent the better part of 2 months combing through numerous datasheets to find the highest efficiency SMPS for the voltage requirements I had: 5V (bott. left), 3.3V (mid. left), and 14V (top left). This was the result of needing such a power plant.

Work hiatus

April 18th: Fine tune ICSP, place passives and adjust routing, added oscillator, undid I2C work due to oscillator placement

April 19: MicroSD card layout, more attention to passives, routed the 3 I2C components (temperature & barometer, accelerometer, and digital pot), and began looking at where ground planes needed connecting with vias

April 21st: ripped up traces to prep for proper component sizing of SMPS parts and went back to my recorded documentation to see how much current per rail I needed.

April 22nd: Quickly determined that my initial power calculations were being overshot. I don't think it's wise to try and pull 2.3-2.6 Amps from a 2 Amp IC, right? This lead to reshuffling everything based on how much current it needed and which subsystem it got it from. Due to other changed it turned out that I did not need much umph in the 5V rail and the 3.3V rail needed to be beefed up. Looking back and the Doniol gauge, I noted that he used a SOT-223 part labeled L2AA. I quickly found out that LDO regulators had variations where they functioned like boost regulators. Despite my original goal of efficiency, I opted to adjust to having a 12/14.4V to 3.3V SMPS for the main components, have the same input drive the 5V rail via an LDO (ZLDO1117-ADJ) and have the 14V rail driven from the 3.3V rail with the same LDO. Started rearranging the layout for space conservation too.

April 24th: Rotated the layout 90˚ CW, revised MicroSD card slot to a smaller and more readily available part, added placeholder components for CAN & USB, decided to remove LED indication lighting of the analog inputs.

May 2nd #1: Replaced mDP receptacle for one that isn't end-of-life, had to revisit the pinout of the mDP receptacles, removed digital potentiometer and opted for a passive/active combination of accent/backlight control w/ PWM, re-routed analog inputs dropping trace length by up to 33%, re-routed and matched lengths of SPI connections.

May 2nd #2: Debating the move of the SMPS as noted in my previous log. Haven't finalized it's location, but everything seems to fit better this way and it cleaner as a result (less jumping around with vias). I have room for adding circuit protection on the inputs and power connection.