Is it worth it...? We're at 4x as it is, 6x can be accomplished with the 4x cases (A, B, -A, -B, 2A, and 2B) and the addition of 4A and 4B (and maybe their inverses).

It appears that 4x isn't perfectly-spaced... in fact, the crossover of 2A and B is somewhere around the midpoint of 1/2 and 2/3 of the 2x case... so adding 4A/B to get 6x (rather than upping to 8x) kinda makes sense.

More code, is it worth it...?

(8x would require 1/2 A and 1/2 B...)

All this multiplication can be handled by shift, *if* signed-shift is defined (which is debatable). 2* is a single shift, which is no prob for most uC's, 1/2A likewise. 4*, though, would be two shifts... some uCs might implement arbitrary-shifting in a single CPU cycle, so 4* would be just as quick as 2* on those uCs, but e.g. AVRs have single-shift operators, so 4* would require two CPU cycles... and... 2* can also be implemented as A+A, which is usually a single cycle instruction... Of course, this all gets a bit more complicated if, e.g., the ADC's are 10-bit and the architecture is 8-bit...

And, again, I'm not sure signed-shift is well-defined and architecture-independent.

So, contemplations...