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60 Results for "rtl-sdr"

  • Identifying the components

  • So, time to identify what I have to work with. First the nixies. I had forgotten but there are only 5 numeric nixies, the rightmost 5, which are type ZM1000. The leftmost nixie is a symbol nixie ZM1001 which can display X, Y, Z, +, - and the sine wave...
  • Hack Chat Transcript, Part 2

  • James Aguirre12:17 PM@0xCoto that's great stuff! Canadian Centre for Experimental Radio Astronomy12:17 PM@Dan Twedt my first paper on SDR radio astronomy was about SETI back in 2004. Dan Twedt12:18 PMThat's awesome! A good magnet to the hobby! 0xCoto12:18...
  • Exit MIG, Enter LiteDRAM.

  • LiteDRAM in the BoxLambda Architecture. Initially, the plan was to use Xilinx’s MIG (Memory Interface Generator) to generate a DDR Memory Controller for Boxlambda. At the time, that was (and maybe still is) the consensus online when I was looking for...
  • Hack Chat Transcript, Page 1

  • Dan Maloney12:00 PMOK, let's talk satellites! I'm Dan, I'll be modding today along with Dusan for Nathaniel Evry from Quub, Inc as we talk DIY PIcosatellites. Apologies in advance for my wonky keyboard with the stuck spacebar, BTW hkurz12:00 PMhi Dan...
  • Hack Chat Transcript, Part 2

  • James Finch12:34 PMRainbow Photonics AG is who I am thinking of. David Troetschel12:35 PM@James Finch oh, this looks cool! James Finch12:35 PMW-Band is interesting. The Signal Path12:35 PM@David Troetschel (Power Factor (loss Tangent) @15°C: 0.0001...
  • XOR Gates

  • As a next step we will look into options to design XOR2 gates in LTL. A straightforward approach is to build a XOR2 gate from 4 NAND gates. This is simple and robust, but results in a propagation delay of three NAND2 equivalent. Not perfect for fast...
  • Validating Actual Hardware

  • The PCB in all its glory Validation First step is to test the clock generation. The scope image below shows how the CD4017 generates the nonoverlapping two phase clock (clk and clk_n) from the input clock signal. It appears that the CD4017 is able to...
  • Hello Debugger!

  • Recap Here’s a summary of the current state of BoxLambda. We currently have: A test build consisting of an Ibex RISCV core, a Wishbone shared bus, internal memory, a timer, two GPIO ports, and a UART core.A simple Hello World and LED toggling test program...