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336 Results for "《〈 문의 OIO↗5793↗7458 》〉강남초원의집㉩⅓everythingァ강남유흥강남룸㏁evidently 강남초원의집강남더킹 강남더킹‡강남룸Ⅹfaintly㈆"
FPGA-based GPU as high speed learning platform
Project
by
Ian Hanschen
FPGA-based GPU and sprite engine with burst optimized design, implemented across several FPGA platforms and memory systems.
38
28
WS2812B Delay Splitter
Project
by
Pete
Splts a WS2812B bitstream, delaying one side by a selectable number of LEDs
7
7
FPGA DES Cracker
Project
by
Pontus Rodling
Learning project for FPGA development implementing a parallelized DES-cracker and Linux kernel drivers on a Altera DE2i-150 FPGA board
1.7k
9
FPGA S/PDIF Digital Audio Mixer
Project
by
Pontus Rodling
Digital audio mixer using S/PDIF implemented on an FPGA
1.8k
5
Bexkat1 CPU
Project
by
Matt Stock
A custom 32-bit CPU core with GCC toolchain
63
51
FPGA Doom
Project
by
Matt Stock
Porting the classic Doom engine to an FPGA-based system
69
57
Mechanical Sunflower with stepper motor and FPGA
Project
by
Sarp Köksal
Stepper motor works with the idea of sunflower which turns toward the light
4
5
yapg
Project
by
Evan
yet another pixel globe
202
116
BabyBaby or Extremely Small Experimental Computer
Project
by
dave
An FPGA implementation of the Manchester Baby or Small Scale Experimental Computer.
3.3k
39
Icestudio
Project
by
Jesús Arroyo Torrens
Experimental graphic editor for open FPGAs. Built on top of icestorm project.
36
23
Kestrel Computer Project
Project
by
Samuel A. Falvo II
The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.
316
81
Distance measurement with 3D camera
Project
by
JS
Distance measurement using 2 cameras and triangulation
1.4k
10
FPGA-based camera vision for everyone
Project
by
dennisvanelteren
Always wanted to unleash the power of an FPGA chip? Interested in robotics and vision? Then this might be the project for you!
4.1k
34
OpenECG
Project
by
Alex Lungu
A wearable, high-performance ECG device, aimed at heart patients, athletes and more
90
61
muCPU: an 8-bit MCU
Project
by
Reed Foster
An 8-bit load-store CPU with 2 pipeline stages, designed in Logisim and implemented in VHDL + assembler written in Python
44
35
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