75 Results for "↘ 최저가 Ò1Ò〈⑻⑷89〉83Ò⑥ ↗퍼블릭술집τ퍼블릭사이즈resist강남퍼블릭강남퍼블릭셔츠룸퍼블릭autumn 강남퍼블릭Ⅷ㎱셔츠룸퍼블릭dread"

ProAsic3-Stamp
Project by Antti Lukats
Stamp Style PCB with ProAsic3 FPGA
- 606
- 15

microYasep
Project by Yann Guidon / YGDES
a configurable 16-32 bits MPU in VHDL for tiny FPGA
- 910
- 15

YASEP Yet Another Small Embedded Processor
Project by Yann Guidon / YGDES
YASEP is the architecture/ISA of a 16/32 bits microprocessor that is original, Free, configurable, compact and ideal for DIYers, teaching...
- 28
- 19

FPGA Sound Sampler
Project by Reynarduino
An FPGA-based sampler inspired by the Casio SK and Yamaha VSS series samplers.
- 127
- 5

Kortex-S Processor
Project by Antti Lukats
Bit serialized ARM Cortex Processor
- 15
- 15

Recursive Range Reduction (3R) HW&SW CODEC
Project by Yann Guidon / YGDES
A high speed circuit design in JS and VHDL for decoding 3R bitstreams, a "quasi-entropy" code that compacts series of correlated numbers.
- 14
- 27

FPGA Tips
Project by Antti Lukats
FPGA: What they are when to use and when not and if then how?
- 95
- 56

FPGA computer
Project by Dylan Brophy
I am building a (currently) 64k RAM computer with an FPGA. Now with lots of pipelining!
- 39
- 34

HDMI2USB.tv Open video capture hardware + firmware
Project by Tim Ansell
The HDMI2USB project develops open hardware to record and stream HD videos (from HDMI & DisplayPort sources) for conferences and usergroups.
- 2.5k
- 21

40-channels RGB LED strings driver
Project by Yann Guidon / YGDES
A subset of the WizYasep that unleashes all the 40 outputs and drives 3.2Mbytes/s of asynchronous RGB LED strings with no effort.
- 3
- 4

BabyBaby or Extremely Small Experimental Computer
Project by dave
An FPGA implementation of the Manchester Baby or Small Scale Experimental Computer.
- 3.3k
- 39

The 'Configum' module
Project by Kn/vD
A full FPGA system in one square inch area
- 31
- 34

CPU7
Project by Kn/vD
A concept for a small RPN processor with interesting features
- 129
- 22

muCPU: an 8-bit MCU
Project by Reed Foster
An 8-bit load-store CPU with 2 pipeline stages, designed in Logisim and implemented in VHDL + assembler written in Python
- 44
- 35

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