33 Results for "『 모든문의 OIO=5793=7458 』 선릉셔츠룸㈄『 모든문의 OIO=5793=7458 』 Ηcake²셔츠룸테란강남셔츠룸デwriter 셔츠룸테란강남셔츠룸 선릉셔츠룸⒁셔츠룸사이즈┲exhausted⅔"

JF2020-1
Project by Justus Hausmann
Designed a new Processor, based on the things I learned from my smlCPU. Currently working on a user-friendly(ish) simulator for it.
- 104
- 5

The NEORV32 RISC-V Processor
Project by Stephan
An easy-to-use, customizable, lightweight and open-source 32-bit RISC-V microcontroller/CPU written in platform-independent VHDL.
- 50
- 33

C70100 GPU
Project by Dylan Brophy
The Goal: 3D rendering on an FPGA
- 4
- 6

The Moncky project
Project by bigbat
Creating a complete working retro 16-bit computer from scratch in the style of the C64, CPC 464 and alike using an FPGA
- 30
- 24

BADGE FOR SUPERCON.6 / November 2022
Project by Voja Antonic
After three years... Supercon again! And the new badge too!
- 181
- 161

Centipede Processor
Project by Kn/vD
Another one of them "crazy processors", just a bit crazier
- 5
- 4

The "L7" A very simple 8 bit CPU
Project by Myk Dormer
Another retro CPU project. The most primitive design I could think up
- 4
- 4

16 Bit CPU in Verilog HDL
Project by talha
A very minimal pedagogical 16 bit processor based on the Harvard Architecture
- 1
- 1

S.A.M.I.R.A.
Project by 0xCAFEAFFE
Synchronous All-Purpose Minimal Instruction Reckoning Apparatus
- 79
- 59

Brick-Breaker Game using NIOS II on FPGA
Project by Sarang Nerkar
Brick-Breaker Game using the NIOS II processor on Altera's DE2 Board.
- 6
- 2

DDC-01
Project by Johnny B. Goode
A processor from discrete components.
- 9
- 5

microYasep
Project by Yann Guidon / YGDES
a configurable 16-32 bits MPU in VHDL for tiny FPGA
- 910
- 15

Discrete YASEP
Project by Yann Guidon / YGDES
a 16-bits YASEP computer (mostly) made of DIP/SOIC chips like in the 70s and 80s... with 2010's twists!
- 81
- 78

NEDONAND homebrew computer
Project by SHAOS
NEDONAND is 8-bit homebrew computer entirely built out of many 74F00 chips (2-input NAND gates)
- 162
- 130

32 bit MIPS CPU
Project by Reed Foster
A five stage CPU core based on the MIPS instruction set
- 2k
- 26

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