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17 Results for "↘ 최저가 Ò1Ò〈⑻⑷89〉83Ò⑥ ↗ 쓰리아워가격u 쓰리아워가격earth강남쓰리아워강남쓰리아워쓰리아워enter 강남쓰리아워ぶЪ강남쓰리아워most"
Custom parallel processors in Verilog/FPGA
Project
by
Bruce Land
Each custom CPU is a stack machine. Parallel computation is via shared memory. I wrote a stack language compiler for the CPU.
95
53
Chemical Reaction Solver in Verilog -- NO ODEs!
Project
by
Bruce Land
Chemical reactions modeled by counting particles and using random numbers to see if a reaction occurs. NO differential equations!
50
26
FPGA Simulates Analog Computer
Project
by
Bruce Land
Analog computers are completely parallel. FPGA simulation of analog components implements fast, parallel solution of differential equations.
86
39
Teaching FPGA parallel computing
Project
by
Bruce Land
Cornell ECE 5760 teaches FPGA design for DSP, video, and embedded control. Emphasis on parallel computing.
238
110
firstFPGA
Project
by
Arduino Aficionado
This is my first lab with the DE0-nano FPGA board running on Quartus II software.
315
4
DE1-SoC CycloneV experiments
Project
by
Bruce Land
The programming model I wish to use in ece5760 is LINUX running on the ARM processors, talking to hardware on Intel/Altera/Terasic board.
2.4k
18
ARM/FPGA graphics, sound and IPC on DE1-SoC
Project
by
Bruce Land
Using two ARM processors with InterProcess Communication (IPC) to display time while writing video and playing a tone on the FPGA hardware.
443
16
Matlab-to-FPGA UDP communication
Project
by
Bruce Land
DE1-SoC ARM cores running Linux make ethernet communication to the FPGA relatively easy.
316
23
Verilog Bus-masters in Qsys on DE1-SoC
Project
by
Bruce Land
Qsys is Altera's interconnect tool for the FPGA Avalon bus and the ARM9 AXI bus. The ARM9 is a bus-master. I want bus control from the FPGA
24
17
FPGA SoC ARM-VGA graphics
Project
by
Bruce Land
The ARM cores on the DE1-SoC have a AXI-Avalon bus connection the FPGA VGA controller. How fast can we make it go?
1.3k
25
Memory on Cyclone5 FPGA
Project
by
Bruce Land
The memory systems of Altera Cyclone5 FPGAs have various features and limitations. I will not talk about the HPS here, only the FPGA.
19
16
Fast FPGA Polygon processor for ARM
Project
by
Bruce Land
This is a start at making a graphics coprocessor for the on-chip ARM9 cpu on Cyclone5 FPGA.
14
11
FIFO interface between ARM and FPGA on DE1-SoC
Project
by
Bruce Land
A FIFO between the Cyclone5 ARM9 and the the FPGA fabric is a convenient way to abstract away communication between them.
28
24
Cyclone5 VGA16-bit color ARM interface.
Project
by
Bruce Land
The "DE1-SoC University computer" IP which ships with the DE1-SoC is 320x240 resolution. This is a conversion and simplification to 640x480.
16
11
FPGA, Floating Point, differential equation solve
Project
by
Bruce Land
The FPGA uses a custom floating point to implement integrators, and all the arithmetic necessary to solve ODE under ARM9 HPS control.
15
13
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