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6 Results for "%EA%B0%95%EB%82%A8%EC%85%94%EC%B8%A0%EB%A3%B8%E3%80%8Eoio_%EF%BC%94%EF%BC%96%EF%BC%94%EF%BC%98_%EF%BC%90%EF%BC%99%EF%BC%93%EF%BC%90%E3%80%8F %E2%88%8F%EC%84%A0%EB%A6%89%EC%85%94%EC%B8%A0%EB%A3%B8 %3E%EC%84%A0%EB%A6%89%EB%A0%88%EA%B9%85%EC%8A%A4%EB%A3%B8%E2%88%88 %EA%B0%95%EB%82%A8%EB%A3%B8%E2%88%82 %EC%84%A0%EB%A6%89%EC%9C%A0%ED%9D%A5%E2%88%81 %EA%B0%95%EB%82%A8%EB%A3%B8%EC%8B%B8%EB%A1%B1%3C %EA%B0%95%EB%82%A8%EC%9C%A0%ED%9D%A5%E2%88%80 %EC%84%A0%EB%A6%89%EB%A3%B8%EC%8B%B8%EB%A1%B1%C2%B1 %EC%84%A0%EB%A6%89%EB%9E%80%EC%A0%9C%EB%A6%AC %E2%88%86%EA%B0%95%EB%82%A8%EB%9E%80%EC%A0%9C%EB%A6%AC every"
SIFP - Single Instruction Format Processor
Project
by
zpekic
A super-scalar, reduced instruction set processor where microcode and machine code are the same thing!
10
10
TMS9900 compatible CPU core in VHDL
Project
by
Erik Piehl
Retro challenge 2017/04 project to create a TMS9900 compatible CPU core. Again in a month... Failure could be an option...
44
35
Libre Gates
Project
by
Yann Guidon / YGDES
A Libre VHDL framework for the static and dynamic analysis of mapped, gate-level circuits for FPGA and ASIC. Design For Test or nothing !
16
11
ARISC 32-bit microprocessor
Project
by
mateuszo
Project include design of microprocessor, assembly language and compiler.
2k
13
VHDL library for gate-level verification
Project
by
Yann Guidon / YGDES
Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries
17
18
hackmac
Hacker
I'm a Bit ghost. Not visible for all (so no photo) but looking around.