Overview:

I was recently working on a schematic that includes some digital isolators (ADUM3480). For power sequencing reasons, I need to operate the chip with the input side powered while the output is unpowered. My concern is… will the signals couple through from the input (powered side) to the output (unpowered) side?

The datasheet (here) doesn’t clearly define this quasi-unpowered behaviour, so I thought it best to do some testing. And, while I’m at it, I may as well document my findings.

TLDR:

If the output is unpowered, then no notable activity will be observed at the output, regardless of what signals are being sent at the input side.

The general test setup / procedure is as follows:

1. Configure device on breadboard… 100nF decoupling for all PWR pins. V_{DDL1}, V_{DDL2}, V_{DD1}, V_{DD2}, V_{DDC1}, and V_{DDC2}.
2. Tie all unused inputs to GND_{1} via a 10kohm resistor
3. Power input V_{DDL1} and V_{DD1} at 3.3V to 5V, and power output V_{DDL1} and V_{DD1} at 3.3V to 5V
4. Apply square wave to one input channel V_{Ix}
5. Observe all pins on output (isolated side)
6. Disconnect the output power from V_{DDL2} and V_{DD2} and repeat step 4/5

Test gear used:

1. Isolated PSU – BK Precision Model 1670 DC Power Supply (3 isolated channels)
2. Function Gen – SDG 1032X
3. Oscilloscope – SDS 1104X

Results:

The initial sanity check confirmed the chip was functioning normally (step 3 to 5). The 3V3 input signal, and 5V output are shown below. Note these two signals couldn’t be captured in the same image since I don’t have isolating probes… and I didn’t want to short the two isolated GND’s.

Figure 1 - Input signal

Figure 2 - Output Signal

Next, I disconnected the 5V supply at the output, while leaving the input 10kHz square wave on V_{IB}. The output channel V_{OB} is shown below. We can see minor activity at the output (periodic spikes), likely caused by capacitive coupling.. since these spikes correspond to the edges of the input signal.

Figure 3 - Input Powered, Output Unpowered, Output signal

Next, I repeated the test with an input voltage of 5V, hoping to provide a worst case for capacitive coupling. There was a negligible change from the 3V3 test.

 Caveats of these results:

Reminder that this test was conducted without any forced potential difference across the isolation barrier. I'm not sure how a 1kV difference between GND_1 and GND_2 might affect these results. I would think the results would be much the same, but I'm not very well versed in high voltage design.