BTB-1 IS a mysterious project. IT SIMULATES retriggerable, back-to-back monostable circuits. TRIGGER USES an inherent fact of comparator design, the delay ascribed as being asserted when logic becomes briefly contentious, instable. I use it as the trigger. Two stages retrigger each other during momentary instability with small capacitively coupled spikes, barely enough to cause runaway & a trigger which cannot occur with direct DC coupling between stages. NOW, IT has occurred to me that I should look for a way to assert THREE back-to-back stages. IF PODSIBLE, the third would allow for an EXECUTION period, analogous to the 'data valid' duration in digital bus clocking. After SYNC, & DELAY, there could be the EXECUTION period to assert intended results from logical & event confluence. NEXT TRIGGER would synchronize. BTB-1 is demonstrated in very low frequency clocking.