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PCB Design Perfection Starts in the CAD Library

plaquelambdo410991plaquelambdo410991 wrote 03/07/2019 at 11:17 • 4 min read • Like

Drafting elements in a CAD library part are not “Standardized” for specific values or sizes but there are recommendations that are coming out in the IPC-2610 series that include schematics, PCB assembly(PCBA) and fabrication. Documentation includes component outline and polarity markings for silkscreen and assembly. This article focuses on silkscreen and assembly Reference Designators.
 Every reference designator (Ref Des) originates in the schematic diagram and is transferred to the PCB layout via the netlist. They also appear in the Bill of Material that is exported from the schematic and passed to the assembly shop. The rules for reference designator assignment are established by the IPC-2512 publication. However the Ref Des size, font, CAD layer and placement location are left up to the EE engineer and/or PCB designer.
 Every CAD library part should have 2 distinct reference designators, one for the silkscreen and one for the assembly drawing. Both designators, in every CAD library part, are normally located in the center of the component body. The silkscreen reference designator is relocated outside the component body after the part placement is completed and approved by the design review panel. If via fanout and trace routing cause part placement nudging then it’s best to wait until that process is completed or duplication of effort will come into play. Also, if via hole sizes exceed 0.4 mm and they are not tented then it’s best to avoid placing the silkscreen reference designators over the via hole, as the ink will drop into the hole making the reference designator indistinguishable and eliminate the purpose of having the reference designator to begin with. If you are using large via hole sizes it’s best to wait until the PCB design passes the engineering routing review panel. Via sizes smaller than 0.4mm can be tented (covered) with solder mask and the placement of silkscreen designators can go directly on the via.
 The silkscreen reference designator height sizes are –

 The reference designator text line width is normally 10% of the height for good clarity and to prevent the characters from bleeding or blobbing together. The 0.15 mm height “Default” is what the LP Calculator uses but users can change the global setting values to any value or measurement system.
 The assembly reference designators are different in the fact that they never get relocated outside the component body outline. Assembly reference designator height sizes are –

 Here are some chip component assembly ref des height sizes that scale down according to the body size  –

 Note: All assembly body outlines are 1:1 scale of the physical component with the exception of all micro-miniature parts smaller than 1.6 mm length. Parts less than 1.6 mm length are EIA 0402 and 0201. These 2 parts assembly outline has to be enlarged so that the 0.5 mm assembly ref des fits cleanly inside it.
Also, most land patterns (CAD library parts) have the Lands (Pads) put on the assembly layer. This is true for all parts that are large enough to accommodate both the component leads and the assembly ref des without interfering with each other. When the component leads interfere with the assembly ref des, the component leads on the assembly layer are removed from the padstack. This includes all chip components, crystals, molded body parts and grid array parts with bottom only leads.
See Figure 1 for a sample of a typical silkscreen with the reference designators relocated outside the part.
figure-1-example-of-silkscreen-ref-des

 See Figure 2 for a sample of a typical assembly drawing with the reference designators inside the part, exactly where they were put when the CAD library parts were built. While the silkscreen reference designators must be relocated to an optimized location after part placement is completed, the assembly reference designators do not require any movement or cleanup. Also notice in Figure 2 that the large parts have lands (pads) built into the padstack and the small chip components do not have lands (pads) on the assembly layer. The LP Calculator allows the user to turn on/off Land on Assembly because some people do not want any component leads on the assembly drawing; rather they only want closed polygons with reference designators inside.
figure-2-example-of-assembly-ref-des

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