The Chameleon Arduino-compatible shield board was designed to support two general application areas: (1) soft-core processors, and (2) intelligent serial communications interface. The board was constructed to be compatible with the form-factor of the Arduino UNO. A similar design uses a form-factor suitable for use in a Pac-Tec DIN-rail enclosure. The Arduino UNO form-factor is small and popular with students and hobbyists. Although, the Arduino UNO form-factor may not be ideal for industrial applications, its small size makes it rugged enough for many industrial applications.

The small form-factor also presents a challenge. The greatest challenge in implementing the Chameleon for its intended applications was to keep the on-board features to those that would provide the greatest utility if the board was used in a standalone manner in addition to being used as an Arduino shield. In addition, although surface mount technology (SMT) would be required to implement the Chameleon, every effort was made to use SMT parts that a hobbyist could install by hand and a soldering iron. (The Chameleon board pictured was assembled by hand and a soldering iron.)

Thus, the VQ100 package was selected for the FPGA because it is the smallest QFP package from Xilinx which supports multiple FPGAs: the Spartan 3A XC3S50A-4VQG100I and XC3S200A-4VQG100I FPGAs. Interestingly, the board area used by the VQ100 package is also the same as the board area of the FG256 (BGA) package. All members of the Spartan 3A family are packaged in the FG256 or FT256 package. The BGA package will be used in more advanced versions of the Chameleon.

However, for this project cost and ease of assembly were the driving factors. Thus, only the XC3S50A and the XC3S200A in the VQ100 package were considered. Either FPGA may be used on the Chameleon. For an effective soft-core processor platform, the XC3S200A FPGA is a much better choice than the XC3S50A. The soft-core processor that I've already developed and proven on a similar FPGA development board, the M65C02, will fit in the XC3S50A FPGA. However, the complete 65C02-compatible core will utilize more than 50% of the logic and 2/3 of the block RAMs available in that FPGA. Thus, there would be few resources left in that FPGA to include on-chip RAM or peripherals such as UARTs, SPI masters, timers, etc. If the XC3S200A FPGA is used, then the M65C02 core can be incorporated along with two buffered UARTs (with 16 byte Rx/Tx FIFOs) and a buffered SPI master (also with 16 byte Tx/Rx FIFOs). This configuration of soft-core processor and peripheral uses only 50% of the XC3S200A FPGA, which leaves plenty of logic resources available for any additional peripherals or increased FIFO depths.

Beyond the FPGA, a commonly required interface for industrial or hobby projects is a simple RS-232 or RS-485 serial port. For this reason, the off-board I/O capabilities of the Chameleon are focused on serial communications. Supporting both RS-232 and/or RS-485 is a definite plus. It is not generally necessary to support software configuration of the interface's signalling protocol: separate RS-232 and RS-485 transceivers are sufficient. Multi-protocol chips such as those available from Sipex are not necessary, and a simple cable to select the appropriate channel is a much lower cost alternative. It is for this reason that 4-wire full-duplex RS-232 (TxD, nRTS, RxD, and nCTS) and a 2-wire half-duplex RS-485 are supported on the same connector.

Placing two DB-9 connectors on the small Arduino UNO form-factor for these two serial ports is not possible. Therefore, these the Chameleon's two RS-232/RS-485 serial ports are implemented using two 2x5 box headers. These box headers allow the use of low cost 10-pin ribbon cable to make the interface cables. A 10-pin insulation displacement (IDC) plug connector and a 9-pin IDC DB9-F connector can be crimped onto a low-cost 10-pin ribbon cable. The resulting cable provides a low cost serial port connection. In addition, these headers configured to support the DB9F Data Communication Equipment (DCE) pin out. Choosing this configuration allows a standard DB9M-DB9F serial cable to be used to connect the Chameleon's serial ports to other equipment. (Most equipment support the Data Terminal Equipment (DTE) pin out.)

The XC3S50A and XC3S200A FPGAs have configurations which are held in volatile memory elements, i.e. latches. Thus, when power is turned off, the HW design they implement is lost, and must be reloaded from some type of external non-volatile memory or by a processor. (Using the Arduino UNO to hold the configuration of the FPGA in its program memory would be a fantastic waste of a scarce resource; the program memory of the Arduino UNO is better utilized for user sketches.) Spartan 3A FPGAs can be configured from application-specific serial configuration memories available from Xilinx/Atmel, parallel Flash EPROMs, SPI Flash (available from Spansion, Winbond, Atmel, etc.) or JTAG. (JTAG is not a good solution for the applications for which the Chameleon is intended, but the Chameleon includes a JTAG programming header for development and debugging.) The application-specific serial configuration memories from Xilinx/Atmel are expensive and should not be used because the Spartan 3A FPGA family directly supports industry standard SPI Serial Flash parts which are much less expensive, available in larger sizes, and available from multiple vendors. (Furthermore, there is every indication that Xilinx is not looking to provide new proprietary configuration memories for its FPGAs. This interpretation of their intentions is based on the fact that all new FPGAs released by Xilinx since the release of the Spartan 3A family have included built in support for industry standard SPI Serial Flash.)

The Chameleon's SPI Flash memory provides much more storage than required for the configuration image of the FPGA. The remaining memory is available for the user. After configuration the pins used to read the configuration image may be used by the user for other functions, but the Chameleon's FPGA design retains those four pins as an on-board SPI bus for use by the user. In addition to the serial Flash, the Chameleon includes a second serial memory device on the SPI bus: a 4kb Ferro-electric RAM (FRAM).

The buffered SPI master interface peripheral function provided in the project provides an easy way for user programs in the projects soft-core processor to access programs and data stored in these two external serial memory devices. The SPI master interface peripheral has been kept as simple as possible, but it includes FIFO buffers on both transmit and receive. The FIFOs simplify the soft-core driver firmware, and allow them to be written to use interrupts. The SPI peripheral function consists of a control/status register and transmit/receive holding registers (FIFOs). The control/status register provides a simple means for changing the SPI clock rate and for selected 1 of 2 external devices. One unique feature of the Chameleon's SPI peripheral is that it allows the user to control whether the serial input data is captured or discarded. This allows the user to write to the external devices without having to clear the input FIFO. The depth of the SPI peripheral's FIFOs are independently parameterized so that the user can easily synthesize a new design with whatever depth is needed for a particular application.

The UART peripherals used in the Chameleon are also buffered like the SPI peripheral. The UART peripherals are specifically designed to support several serial communication modes: (1) two-wire RS-232, (2) 4-wire RS-232, (3) half-duplex RS-485, and (4) half-duplex RS-485 collision detection. In the two-wire RS-232 mode, the UART transmits and receives data without handshaking in a full-duplex manner. In this mode, the RTS and CTS signals may be controlled and monitored using the control and status registers of the UART. In the 4-wire RS-232 mode, the UART performs RTS/CTS handshaking. During receive operations, it will automatically deassert RTS when the receive FIFO is above a fixed threshold. During transmit operations, the transmitter waits until CTS is not asserted before sending any data. If CTS is asserted during the transmission of a character, then the UART will discontinue further transmission after the transmission of the current character's stop bit. The UART peripherals also include a programmable receive timeout (RTO) function. To avoid polling of the FIFO state in the RS-232 modes, this function is used to generate an interrupt in the event that the far end stops transmitting and the FIFO threshold has not been exceeded.

The half-duplex RS-485 mode forces the RS485 RxD input to the mark state internally, and the half-duplex RS-485 collision detection mode processes the RxD signal normally. (The receive function of the Chameleon's RS-485 transceivers is always enabled. Fail-safe biasing on the differential signal pins ensures that the RS-485 RxD is in the mark state when the network is unconnected or undriven.) With the RS-485 collision detection mode it is possible to verify that messages are sent without collisions (at the near end). Thus, it is possible to implement collision detection multiple access (CDMA) RS-485 networks with multiple masters using the collision detection mode of the UARTs.

The RTO function is used in the RS-485 modes to regulate when the transmitter starts, i.e. the RTO function acts like the CTS signal of the 4-wire RS-232 mode. If there is data in the transmit FIFO, and RTO is asserted, then the RS-485 OE signal is asserted and the data is transmitted. (A delay of 1 bit time is automatically imposed in the RS-485 modes after the driver is enabled to ensure a good start bit.) At the end of the packet, the transmitter automatically deasserts the RS-485 OE signal. The RTO function is also automatically started at this time. This allows the RTO function to be used to automatically frame RS-485 protocols that require a minimum inter-frame gap such as Modbus RTU. Using the RTO function in this manner for the RS-485 modes simplifies the implementation of a number of industry standard protocols: Modbus RTU and Profibus.